LSI とシステムのワークショップ2019　ポスターセッション発表概要

An ultra-low-power atomic clock based on CMOS probing and locking loop

○Haosheng Zhang，Hans Herdian，AravindTharayil Narayanan，Atsushi Shirane（Tokyo Institute of Technology），Mitsuru Suzuki，Kazuhiro Harasaka，Kazuhiko Adachi（Ricoh），Shinya Yanagimachi（National Institute of Advanced Industrial Science and Technology），Kenichi Okada（Tokyo Institute of Technology）

A highly stable and ultra-low-power frequency standard is essential for field deployment and portable devices. The paper introduces a chip-scale ultra-low-power atomic clock (ULPAC). By synchronizing to an atomic resonance, the crystal oscillator output frequency is continuously compensated and stabilized. The power consumption of the ULPAC is dramatically reduced by a new suspended quantum package and highly power efficient probing and locking loop. The proposed ULPAC obtains a long-term stability of 2.2x10-12, while consuming 59.9mW.