This paper presents a Fractional-N PLL for IoT applications in 65-nm CMOS. A duty-cycled FLL and an out-of-dead-zone detector were used to switch the feedback path between subsampling and sampling mode to achieve robust phase locking with 150 μW power reduction in the feedback path. A transformer-based DCO with current-reusing technique and a low-power single-slope DTC were proposed to further reduce the power consumption. The proposed PLL occupies an area of 0.25 mm^2 and can achieve an integrated jitter of 2.8 ps under 265 μW power consumption.